1. Field of the Invention
This invention generally relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a non-volatile memory and a metal interconnect process.
2. Description of Related Art
Non-volatile memory devices have been used to store data. Flash memory is one type of the non-volatile memory devices, which is an electrically erasable programmable read only memory (EEPROM) in which data is retained even after all power sources have been disconnected. Flash memory has been widely used in personal computers and other electronic equipment because it can provide the property of multiple entries, retrievals and erasures of data.
A conventional flash memory cell is a transistor with a control gate, a doped polysilicon floating gate and an oxide layer separating these two gates from each other. A tunneling oxide layer separates the floating gate and the substrate. During the programming of the memory, proper biases are applied to the source region, the drain region and the control gate. Electrons would then travel from the source region to the drain region through the channel. During this process, some of the electrons are injected through the tunneling oxide layer into the polysilicon floating gate, and the electrons are evenly distributed in the entire polysilicon floating gate. The injection of electrons into the polysilicon floating gate is known as the tunneling effect. The operation mechanism of a flash memory device includes the channel hot electron injection for programming of data and the Fowler-Nordheim Tunneling for the erasing of data. However, if defects are present in the tunneling oxide layer underneath the polysilicon floating gate, current leakage easily occurs, which affects the reliability of the memory device.
To prevent the flash memory from the current leakage problem, a charge-trapping layer has been proposed to replace the polysilicon floating gate, and the EEPROM is formed with a stacked gate structure comprising a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. The material of the charge-trapping layer is silicon nitride. Hence, this kind of EEPROM is also called silicon nitride read only memory (NROM). Because the silicon nitride layer can trap charges, the injected electrons will not be distributed uniformly in the silicon nitride layer but Gaussian-distributed in the silicon nitride layer. Therefore, the current leakage will be reduced because most of the electrons are localized in small section of the silicon nitride layer, and thus they are insensitive to the defect of the tunneling oxide layer.
Another advantage of using silicon nitride layer is that during the programming process the electrons are stored locally in the channel, close to the source side or the drain side. Hence, during the programming process, the voltage can be applied to the source region and the control gate in one end of the stacked gate, and the Gaussian-distributed electrons are stored in the silicon nitride layer at the drain region in the other end of the stacked gate. The voltage can also be applied to the drain region and the control gate in one end of the stacked gate, and the Gaussian-distributed electrons are stored in the silicon nitride layer at the source region in the other end of the stacked gate. Therefore, by changing the voltages applied to the control gates and the above two regions, there may be two groups of Gaussian-distributed electrons, one group of Gaussian-distributed electrons, or no electrons in a single silicon nitride layer. Hence, the flash memory using a silicon nitride layer to replace the floating gate can be programmed in four states, and such a memory cell is a two bits in one cell flash memory cell.
However, during the fabrication of the NROM, for example, in the PECVD process, the plasma causes the charges to move along the metal, which induces the so-called antenna effect. Hence, in a brief moment, a portion of electrons is trapped in the composite ONO layer such that a wide threshold voltage distribution among memory devices is resulted.
It should be noted that in addition to the antenna effect that leads to a wide threshold voltage distribution, the clustering of the electrons on the surface of the film may result, For example, during the metal interconnect process of the NROM, an insulating layer is formed by the PECVD process to cover the metal lines. The material of the insulating layer is oxide or nitride. However, the plasma used in the PECVD process often causes a clustering of charges on the surface of the insulator layer. These charges then move to the silicon nitride layer in the ONO layer along the metal lines. As a result, a wide threshold voltage distribution among memory devices is resulted.
Further, during the photolithography process, an ultraviolet light is used for exposure. However, in a NROM device, electron-hole pairs are generated in the silicon nitride layer as the silicon nitride layer of the ONO layer being irradiated by the ultraviolet light. Further, because the holes are easily slipped away and only the electrons are left in the silicon nitride layer. Ultimately, a wide threshold voltage distribution among memory devices is resulted.